Field of the Disclosure
The present disclosure relates generally to semiconductor devices and, more particularly, to trench gate field effect transistors.
Description of the Related Art
Vertical transistors, such as trench gate field effect transistors (FETs) frequently are utilized in high-voltage applications. Such transistors often leverage the reduced surface field (RESURF) effect to achieve a relatively low on resistance (RDSon) while maintaining a relatively high breakdown voltage (BVdss). RESURF-based trench gate architectures employ a one-dimensional or two-dimensional array of transistors in an epitaxial layer that overlies a substrate that itself serves as part of a drain electrode structure. Each transistor has an active region, referred to as a mesa that is defined by a trench extending into the epitaxial layer. Well regions are formed in the mesa regions of the epitaxial layer between adjacent trenches, and a source electrode is connected to the mesa regions via source contact region. Conventionally, for an N-type RESURF trench transistor, the well region is provided as a P− well in which an N+ source region is formed adjacent to the sidewall of a corresponding trench. Adjacent N+ source regions for adjacent cells are isolated through the formation of a P+ region between the two N+ source regions in the P− well. The P+ region is formed through the use of an N+ mask over the region that is to become the P+ region during the implant process for the N+ source regions. It is this P+ region that acts as the channel of the vertical transistor. A dielectric layer is then formed overlying the trenches and mesas, and a contact between the N+ regions and the source electrode metallization is formed through etching of a contact opening in the dielectric layer using a source contact mask. P-type RESURF trench transistors may fabricated in a similar manner, but with regions of opposite conductivity types than those used for the N-type RESURF trench transistor.
The masks used in the formation of the P+ region and in the formation of the source contact are subject to various photolithography design rules. The dimensions of the doped regions within mesa regions therefore are subject to the minimum size and spacing rules set forth by these photolithography design rules. The spacing between trenches (often referred to as the “silicon width” or “Sx”) is a primary factor in the extent of the RESURF effect that may be achieved in a trench gate FET design. The conventional approach to trench gate FET design and its reliance on masks for formation of isolation regions and source contacts for the cells of the transistor thus limits the ability to achieve the reduced spacing between trenches and the enhanced RESURF effect that otherwise would result.